The fabrication of ICs involves the formation of features on a substrate that make up circuit components, such as transistors, resistors and capacitors. The devices are interconnected, enabling the ICs to perform the desired functions. Numerous ICs are fabricated in parallel on a wafer. After wafer processing is completed, the wafer is diced, separating the ICs into individual chips. The individual chips are, for example, assembled in a package.
FIG. 1 shows a conventional electronic chip package 100. The package includes a package substrate 110 and an IC chip 150 which includes chip conductive bumps 155 on an active surface 151. The conductive bumps, for example, are formed from solder balls. Such type of chips is referred to as a flip chip. The chip is mounted on a chip mount (or upper) surface 113 of the substrate, with the bumps contacting contact pads thereon. An underfill 161 is provided, filling the space between the chip and substrate. A lower surface 114 of the substrate includes package conductive balls 103 which form a ball grid array (BGA). Upper and lower conductive traces are provided on respective upper and lower surfaces and interconnected by vias 107 in the substrate, facilitating electrical connections between the package conductive balls and chip conductive bumps.
The present invention provides a package which satisfies demands of increased input-output (I/O) densities and operating frequencies with enhanced thermal and electrical performance.